DVCon India 2017 Call for Panels

DVCon India 2017 Call for Panels



The Design and Verification Conference & Exhibition India (DVCon India) is a highly technical conference in India targeting the application of standardized languages, tools and methodologies for the design and verification of electronic systems, embedded systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon India is similar to the successful DVCon United States conference held for over 10 years in the Silicon Valley.

The ultimate goal of DVCon India is to boost the interest, usage and development of electronic system designs. DVCon India is looking for panel topics that are current, have a high-level of interest and offer strong content. Highly qualified engineers are expected to attend the sponsored panels during DVCon India 2017. Panel sponsorship allows companies to reach a captive audience and the opportunity to follow up with them during breaks, at the exhibits, and following the event. DVCon India is a highly targeted venue for engineers addressing major design and verification issues. You can position your company at the forefront of these discussions by sponsoring a panel. Submit proposals by May 19, 2017.

Topics of interest to DVCon India include:

  • Modeling, Design and Verification of complex electronic systems at different levels of abstraction such as Virtual prototyping, Architectural Modeling, RTL, Emulation, HW acceleration, etc.
  • The application of system-level design and verification languages such as SystemC, SystemVerilog
  • Virtual Platform for Embedded Software Development
  • SoC Design Verification using the latest trends and methodologies such as UVM-SystemC, graph-based techniques, portable stimulus across block-subsystem-system all the way up to Post-Silicon
  • The use of SystemVerilog Assertions (SVA), PSL and Formal Verification (Model Checking)
  • Adoption of Universal Verification Methodology (UVM)
  • IP reuse, design automation and integration standards based on IP-XACT, SystemRDL
  • Low-power design and verification using the Unified Power Format (UPF)

General topic areas on Electronic System Level (ESL), Virtual Platform, Verification & Validation, Analog/Mixed-Signal, IP reuse, Design Automation, and Low-power design and verification will be highlighted in tutorials, panels, papers, and poster sessions.

Conference attendees are primarily designers of embedded systems, electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of EDA tools and IP integration solutions. The DVCon India conference attracts a highly skilled user base active in various industries focusing on research and development of automotive, aerospace, consumer, and wired and wireless communication products.

Important Dates

  • May 19, 2017: Panel proposals due.
  • June 27, 2017: Accept/reject notification.
  • July 7, 2017: All panel content due for Conference Program and website: panel title, abstract, panelist names, affiliations, and biographies.
  • September 14-15, 2017: DVCon India conference.

Panel Proposal Process

Panel sessions should not consist of paper presentations, but should have plenty of discussion engaging the audience. Panels are scheduled for 30 minutes either Thursday or Friday (September 14 or 15). DVCon will select which day the panel will be presented. Please make sure that moderator and panelists are available during the conference dates. If multiple panel suggestions are submitted with similar topics, the committee may choose to accept one over the others, to merge the proposed panels, or to reject all of them.

Proposals should be 2-3 pages in length and should contain:

  • The topic, if possible formulated as a provocative question
  • The issues to be discussed, including a short listing of pro and con arguments
  • Short biographies of the moderator and prospective panelists
  • Any special requirements


Feel free to contact Trevor Kearns for questions on the submission process.

DVCon India reserves the right to restructure all panel suggestions.