DVCon India
September 1-3, 2026
The premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits.
Register Now!WELCOME MESSAGE BY GENERAL CHAIR
Shreya Dasgupta, Analog Devices
General Chair, DVCon India 2026
It is my great pleasure to welcome you to DVCon India 2026, taking place September 1-3, 2026, at Radisson Blu (Marathahalli) in Bengaluru, the vibrant hub of India’s semiconductor and design innovation ecosystem. As General Chair, I am thrilled to invite you to join us for what promises to be our most expansive event yet. Building on the success of previous DVCon editions, we are excited to extend the program to three full days—inspired by the robust agendas of previous years. This allows even more...
Vision Talks
Proof, Not Prompt: Why AI Silicon Needs Formal Verification, Not Just AI-Generated Assertions
AI accelerator chips are running hardware verification into a wall. Inside the die, mixed- precision datapaths spanning FP4 to FP32 feed tensor cores and MAC arrays, while memory controllers arbitrate HBM stacks holding hundreds of gigabytes of weights and activations. Network-on-chip fabrics move petabits per second between compute tiles, and UCIe die-to-die links stitch chiplets into a single coherent package. This is complexity that simulation was never built to catch: you cannot randomly stimulate your way to confidence in a state space this vast. With first-time-right silicon at an all-time low of 14%, formal verification is no longer optional for AI silicon. It is the only practical way to catch silent data corruption, deadlock-inducing NoC bugs, or a BF16 divider underflow that quietly drops a required exception flag.
AI now writes assertions faster than any engineer. But who verifies the verifier? Machine-generated properties carry no guarantee of correctness or completeness, and sign-off demands both: no missed bugs, no proofs stuck at shallow bounds, and 100% coverage. Speed without that guarantee simply gets you to a $100M respin faster.
Formal, too, has a reputation to answer for. State-space explosion, inconclusive bounded results, and a steep skills barrier have kept it a specialist's tool for decades. Rigorous proof engineering breaks through all three, making formal normal, scalable, and predictable on the path to full coverage. Axiomise has spent years pioneering these methods in pursuit of one goal: a deterministic yes/no answer for every property. Our domain-centric apps part of the axiomiser® platform can transform otherwise intractable proofs to determined ones within hours. On large NoCs and RISC-V processors, for example, we sign off with more than 99% exhaustive proofs, compressing multi-person-years of verification effort into a few weeks.
In this talk, I will walk through case studies and methodologies for combining AI's speed with the rigor of human proof engineering, because accelerating verification only matters if you are accelerating toward the right answer.
Presenter: Ashish Darbari
Title: Founder & CEO, Axiomise
Transforming Static Sign-Off with Microarchitectural Analysis & AI
Static sign-off is used widely across system and semiconductor design to shift left with RTL and SoC level verification. As design complexity grows, more application domains are requiring static sign-off – including RTL linting, clock domain crossing, reset domain crossing, design for test, connectivity & glitch, and hardware security.
Real Intent CEO Prakash Narai will discuss how a two-pillar technology approach is transforming static sign-off. One pillar involves using generative and agentic AI to accelerate sign-off workflows. The second pillar incorporates Microarchitecture Analysis (MA) technology to infer standard functional components (SFCs), such as FSMs, FIFOs, multi-port RAMs, stacks, counters, and shifters.
MA can be applied to doing microarchitectural integrity verification early in the design process. Further, adding MA’s functional intent context to areas such as clock domain crossing sign-off results in 20X more precise violation reports – lowering the designer review burden by 95 percent.
Presenter: Dr. Prakash Narain
Title: President & CEO, Real Intent
The Future of Verification: One Path to Silicon Confidence
Semiconductor verification is entering a new era. Traditional flows, built for isolated engines and stable design boundaries, are being stretched by software-defined products, multi-die integration, safety and security requirements, power constraints, and AI-driven workloads. At the same time, engineering teams face rising complexity, shrinking schedules, and growing pressure to deliver first-pass silicon confidence.
In this keynote, Abhi Kolpekwar will explore how the industry can move from verification as a late- stage bottleneck to verification as a continuous, connected, and intelligent discipline. The path forward is not simply faster tools, but a new verification model: one that unifies intent, data, engines, and people across the lifecycle; uses AI to reduce coordination overhead; and preserves human judgment where trust and sign-o matter most. The future of verification will be defined by how well we turn complexity into confidence— scaling not just compute, but engineering insight.
Presenter: Abhi Kolpekwar
Title: Senior VP & GM – Digital Verification Technologies, Siemens EDA
Keynotes
Physical Intelligence Needs a New Engineering Stack: Rethinking Architecture and Execution for Intelligent Physical Systems
As AI moves from generating information to interacting with the physical world, semiconductor development faces a new level of complexity. Delivering intelligent physical systems requires the convergence of architecture, hardware, software, AI models, verification, and execution into a unified engineering workflow. This talk explores how the industry must evolve from traditional chip-centric development to an integrated, AI-accelerated engineering stack that enables faster innovation, higher system reliability, and scalable deployment of Physical Intelligence solutions. The session will share perspectives on the future of semiconductor development and the organizational transformations required to build the next generation of intelligent systems.
Presenter: Anil Kempanna
Title: VP, Global Head of Digital Hardware Design, ADI
Agentic AI for Chip Design: Evolving from Coding Assistants to Super Agents
There is no question that AI has already had significant impact on front end design and verification. However, AI solutions, and impact, are still in their infancy. Unlocking the full productivity potential of AI requires up-leveling solutions and leveraging agentic orchestration, multi-agent, EDA harness for iterative workflows and tight integration with fundamental tools and engines. This presentation will explore the potential, proposed architectures, and challenges of building and deploying Super Agents for chip design and validation.
Presenter: Ziyad Hanna
Title: Corporate VP, R&D, Cadence Design Systems
Power. Performance. Proofs: Scaling Formal for the AI-Driven Compute Revolution
AI is driving an explosive rise in custom compute, demanding architectures that balance performance, power efficiency, and security. While hyperscalers rely mostly on proprietary, GPU-centric designs, open-source RISC-V offers a flexible alternative-especially for Edge AI. Achieving optimal performance-per-watt means smarter design: tuning microarchitecture, NoCs, floating-point precision, and storage with HBMs and caches. In this talk, we present a breakthrough approach from Axiomise to scalable formal verification, combining abstraction-based methods with custom tool automation. Our solution addresses the full spectrum of challenges in verifying custom silicon, including PPA trade-offs and complex floating-point logic. Using mathematical proofs, we detect deep bugs, deadlocks, and livelocks-delivering formal at scale for the AI era.
Presenter: Hitesh Garg
Title: Vice President and India Managing Director of NXP Semiconductors
Generative AI: Is it Real or Merely a Hallucination?
Generative AI is reshaping the landscape of design and verification, but separating genuine breakthroughs from hype remains a challenge. As artificial intelligence becomes increasingly embedded in our daily workflows—from voice assistants to autonomous systems—the question arises: is generative AI delivering real, practical value in chip design verification, or are we chasing illusions? And, with the advent of Large Language Models (LLM) and Generative Pre-Trained Transformer (GPT) models, what are the possibilities in design verification?
This session will examine the current state of generative AI in design and verification. We’ll explore where Synopsys is investing in agentic solutions and what technology is being implemented in production environments by end users, delivering significant productivity boosts and automation. Join us to discover whether generative AI is truly revolutionizing the industry—or if it’s still more hallucination than reality.
Presenter: Pallab Dasgupta
Title: Vice President of R&D Engineering, Synopsys
Industry Talk
Bridging Pre-Silicon Verification to Post-Silicon Debug with Protocol-Aware Tools
As SoCs become more interface-rich, engineering teams need stronger continuity between pre-silicon verification and post-silicon debug. This keynote explores how Prodigy Technovations’ protocol-aware tools help bridge that gap by enabling protocol decode, analysis, traffic generation, error injection and validation across simulation and real silicon environments.
The session will cover Prodigy’s solutions across technologies such as I3C, UFS, PCIe, eMMC, SD, SPMI, RFFE, xSPI, QSPI, SPI, I2C and UART, and how they support use cases from early verification to silicon bring-up, compliance, interoperability and system-level debug.
The keynote will also highlight Prodigy’s the use cases of Protocol exerciser and analyzer in emulation and prototyping environment as well as post silicon validation to reduce the product development and test for customer real world use cases.
Presenter: Vibhav Kaki
Title: Sr. Software Engineering Manager - Prodigy Technovations
AI-powered Chip Design: Spec to Silicon
In today's AI era, chip design is no longer the sole domain of traditional chipmakers. Industry giants - OEMs like Apple and Samsung, and software powerhouses like Microsoft, Amazon, and Meta - are all building their own chips to drive differentiation in products and services. AI is not just enhancing chip design; it's revolutionizing it. From boosting productivity to improving first-time silicon success, AI-powered EDA tools are becoming indispensable. We are witnessing a fundamental shift, where AI is not just an aid - but a necessity that redefines every stage of the semiconductor value chain. As the semiconductor industry enters this bold new chapter, it demands visionary engineers with deep domain expertise - leaders who can drive and shape this AI-led transformation. Join us on this transformative journey as we unlock the boundless possibilities of AI-powered Chip Design, enabling efficient chip design and revolutionizing the landscape of next-generation AI Chips.
Presenter: P R Sivakumar
Title: Founder and CEO, Maven Silicon
AI-Driven Design and Verification: Scaling Complexity with Intelligence
AI is becoming increasingly vital in semiconductor design and verification due to the growing complexity of chips and the need for faster development cycles. AI-driven solutions are under rapid exploration and implementation across the design cycle as they are designed to enhance the scale, speed, and complexity that traditional methods are increasingly struggling with. As chips become more intricate and timelines shrink, the ability to automate repetitive tasks, analyze massive datasets, and predict outcomes with high accuracy is enabling us to utilize AI as a transformative tool to augment design tasks, optimize performance, and predict issues early, enhance test generation, bug detection, and significantly reduce time-to-market.
The talk focuses on opportunities for the convergence of AI into the chip design cycle, specifically focused on the areas of Physical Design and Verification.
Presenter: Jayanth Thimmaiah
Title: Senior Director, Memory Technology, Sandisk
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